What is described are methods and apparatus for storing memory test information. In particular, methods and apparatus for storing memory test information of memory having redundant memory circuitry are presented.
Conventional memory testing involves both an identification of all failed memory addresses in a memory array and an identification of which bit(s) of those memory addresses have failed. A typical memory test involves writing various data patterns into a memory, then reading and comparing the output of the memory with expected values or patterns. Mismatches between expected and actual read memory values are stored in an external memory map, typically located in the memory tester itself.
After all of the test patterns have been executed and the failed addresses (and bits) have been identified and stored, the tester may then perform a repair analysis on the stored error data to determine which failed address rows' and/or columns' (or I/Os) bits (or cells) will need to be replaced with available redundant (or spare) memory cells to make the memory fully operational. The failed memory information is typically analyzed at the end of all of the memory testing. This allows the repair algorithm to take all of the failed memory information into consideration in order to determine an optimal repair configuration that maximizes the operation of the memory and that uses the redundant memory cells in the most efficient manner. In addition, by taking all failed memory information into consideration at one time, certain un-repairable memory conditions may be identified early, and the memory discarded, before wasting valuable test and repair time on the un-repairable situation.
Limitations associated with most conventional testers require that the repair information be generated and used dynamically. This can reduce the overall memory yield by using the redundant memory cells inefficiently. These limitations have also made memory testing a most expensive and time consuming process in the development of faster and denser memory.
For example, conventional memory testers typically have a relatively slower processing clock speed than the operating frequency of the memory cells that they are used to test. The relatively slower clock speed makes it impossible to determine whether the memory under test will operate correctly at normal operating speeds. Also, collecting error information at the normal operating speed is not possible using these slower conventional testers. Consequently, the tester must be capable of storing large amounts of error data and then analyzing this large amount of data in a repair algorithm that is executed “off line”. With conventional testers, the error memory must be as large as the total expected number of failed bits. Moreover, as memory densities continue to increase, the already limited tester memory must also increase and the processing power of the tester must be increased in order to be able to process more complex repair algorithm solutions.
Another limitation associated with conventional testers is their typical limited I/O capability. As memory become more dense, the number of I/Os needed to test the memory must also increase. Testers that are I/O limited will not be able to test the entire memory at one time, requiring that the test program be partitioned into several smaller tests. The partitioning of the memory test leads to an overall increased test time, which contributes greatly to the costs associated with memory manufacture.
Memory designers have utilized built-in-self-test (or BIST) techniques to address some of these concerns. With BIST, a pattern generator for testing the memory is fabricated on the same semiconductor chip (or wafer) as the memory itself. This allows the BIST circuitry to test the memory “at speed”, eliminating the concerns of failing to detect errors as a result of testing memory at sub-operating speeds. In addition, BIST circuitry addresses the concerns associated with today's testers being I/O limited.
Still, limitations exist with conventional BIST techniques. For example, large amounts of error memory must still be incorporated into the BIST circuitry in order to store the failed memory information. Also, additional storage and processor resources must be incorporated into the memory to perform the repair algorithm processing. Because of space and processor limitations, only limited amounts of error storage and repair code can integrated into the BIST design. Consequently, conventional BIST techniques continue to use a “snapshot approach” for detecting failed memory locations. This requires that the repair algorithm process failed memory information “on the fly”, which, as discussed above, leads to an inefficient use of the redundant memory cells included on the memory chip.
Accordingly, there is a need for improved techniques for storing the failed memory information generated from memory testing that will relieve the error storage requirements placed on the tester and that will reduce the complexity of the repair algorithm to a much simpler task. In particular, there is a need for improved techniques for storing only that failed memory information that is necessary to completely analyze and generate the repair information.